The present invention relates generally to tools for computer-aided software engineering. More specifically, the present invention relates to a software-implemented tool for assisting in the design of logic circuits having interconnected circuit elements, the invention providing a technique for checking a user's design against a set of design rules.
Computer design tools are known for assisting circuit designers in the laying out and simulation testing of logic circuitry. One such software base system is that system sold under the trademark MAX-PLUS available from Altera Corporation of San Jose, Calif. Typically, the designer uses such a system to initially design and subsequently test the operation of the design using computer simulation techniques. With reference to FIG. 1, a typical computer logic simulation technique proceeds by initially providing a logic design in the form of a schematic or netlist stored in a file 10 and converting the netlist by means of a logic compiler 12 into a simulator logic netlist 14 that is used by a logic simulator 15. In use, a set of simulation input vectors 16 is also provided to the logic simulator, which reads the simulator logic netlist, along with the simulator input vectors and “simulates” the operation of the logic design by propagating logic levels through the logic primitives in order to generate a set of output vectors 18, which are the simulated outputs of the logic design. This process has been found to be exceedingly useful in the field of logic design, particularly for complex circuits intended for physical implementation in erasable programmable logic devices (EPLDs) and mask programmable logic devices (MPLDs). Recently, with volume applications of circuits, the trend has been to either initially design the logic circuitry with MPLD implementation in mind, or to convert an original design intended for implementation in EPLD form to a functionally identical design intended for implementation in an MPLD form. Typically, a given user's design must conform to a set of design rules governing permitted and prohibited structural and functional configurations, in order for the design to be useful and reliable. Failure to comply with one or a few of the design rules, while not necessarily fatal to the operation of a circuit, can introduce operational uncertainties under special conditions, sometimes with a cumulative effect leading to a partially inoperative or, in extreme cases, a totally inoperative circuit design. While the logic simulation process is intended to reveal erroneous or inconsistent responses to stimulation by the test input vectors, such a result is only obtained after an often lengthy and time consuming simulation of the original design.